DEMO PROGRAM MDT10P22

; ===== DESCRIPTION ========================================================================================
; for IMD101 5X series: 10C22 / 10P22

; ===== REGISTER DEFINITION (RAM MAPPING) ==================================================================



; ......"SPECIAL"...........................................................................................
INDR_ADD EQU 00H ;00H Indirect Addressing Register
RTCC EQU 01H ;01H RTCC
PC EQU 02H ;02H PC
STATUS EQU 03H ;03H STATUS
MSR EQU 04H ;04H MSR
RA EQU 05H ;05H PORT A
RB EQU 06H ;06H PORT B
RC EQU 07H ;07H PORT C






; ......"USER"..............................................................................................
STAGE EQU 08H ;08H
DELAY_1 EQU 09H ;09H
DELAY_2 EQU 0AH ;0AH
TEMP0 EQU 0BH ;0BH
TEMP1 EQU 0CH ;0CH
TEMP2 EQU 0DH ;0DH
TEMP3 EQU 0EH ;0EH









; ===== STATUS DEFINITION ==================================================================================
C EQU 0
HC EQU 1
Z EQU 2
PF EQU 3
TF EQU 4


; ===== OTHERS DEFINITION ==================================================================================
W EQU 0



; ===== MAIN-PROGRAM BLOCK =================================================================================
; ----- 檢查 STATUS 暫存器的 B4(TF) 及 B3(PF), 依 RESET 原因作 DEMO 程式的流程控制 -------------------------
;if TF為是'0': PF為是'0'> 代表 IC 進入 sleep 後被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以進行跳關
; : PF為否'1'> 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至指定的副程式作 WDT 功能檢測
;if TF為否'1': PF為是'0'> 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序
; : PF為否'1'> Power on reset 或程式進行中作 MCLR reset



ORG 00H ; 以下程式碼由 00H 的位址開始存入程式記憶體(ROM)

BEGIN: BTSS STATUS,TF ; check TF 判斷是否被 WDT reset, 0:是 1:否
LJUMP TF0 ; TF=0, IC 被 WDT reset, 跳至 'TF0 副程式'

TF1: BTSS STATUS,PF ; TF=1, IC 未被 WDT reset, check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP PF0 ; ____PF=0, 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序

LJUMP STAGE1 ; ____PF=1, Power on reset, 跳至 'STAGE1 副程式'


TF0: ; 因為 TF=0, IC 被 WDT reset
BTSC STATUS,PF ; check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP TF0PF1 ; ____PF=1, 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至 'TF0PF1 副程式' 進行 WDT test
CLRW
CPIO RA
CPIO RB

SLEEP ; ____PF=0, 代表 IC 進入 sleep 後又被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以跳至 'PF0 副程式',
; 並以 STAGE 暫存器之累加值進行關卡轉換

TF0PF1: CLRWT
LJUMP BEGIN1A ; 跳至 'BEGIN1A 副程式' 進行 WDT test


PF0: LDR STAGE,W ; 將 STAGE 暫存器累加值與目前 PC 值相加
ADDWR PC,1 ; 相加後的 PC 值指向欲測試之關卡
LJUMP STAGE2 ; RAM testing
LJUMP STAGE3 ; RTCC testing
LJUMP STAGE4 ; WDT testing
LJUMP STAGE1 ; I/O testing

; ----- STAGE1 I/O testing ---------------------------------------------------------------------------------
STAGE1: LDWI 10101010B
STWR RA
STWR RB

ANDWI 11111111B
XORWR RA,W
BTSC STATUS,Z
LJUMP FAIL_RAIN
LDWI 10101010B
ANDWI 11111111B
XORWR RB,W
BTSC STATUS,Z
LJUMP FAIL_RBIN






CLRW
CPIO RA
CPIO RB

CLRR RA
CLRR RB


CLRR STAGE
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

CLRR TEMP3
ADDRA: CLRWT
LDR TEMP3,W
ADDWR PC,1
LJUMP RA1H
LJUMP RA3H
LJUMP RA7H
LJUMP RAFH
LJUMP RA1FH
LJUMP RA3FH
LJUMP RA7FH
LJUMP RAFFH
LJUMP IOEND

OUTTEST: CLRR RB

BSR STATUS,C
LOOPRB: CLRWT
RRR RB
LCALL DELAY
BTSS STATUS,C
LJUMP LOOPRB





INCR TEMP3,1
LJUMP ADDRA


RA1H: LDWI 01H
STWR RA
COMR RA,1
LJUMP OUTTEST

RA3H: LDWI 03H
STWR RA
COMR RA,1
LJUMP OUTTEST

RA7H: LDWI 07H
STWR RA
COMR RA,1
LJUMP OUTTEST

RAFH: LDWI 0FH
STWR RA
COMR RA,1
LJUMP OUTTEST

RA1FH: LDWI 01FH
STWR RA
COMR RA,1
LJUMP OUTTEST

RA3FH: LDWI 03FH
STWR RA
COMR RA,1
LJUMP OUTTEST

RA7FH: LDWI 07FH
STWR RA
COMR RA,1
LJUMP OUTTEST

RAFFH: LDWI 0FFH
STWR RA
COMR RA,1
LJUMP OUTTEST

IOEND: CLRWT
INCR STAGE,W
STWR RA
STWR RB

COMR RA,1
COMR RB,1

SLEEP
LJUMP BEGIN

FAIL_RAIN: CLRW
CPIO RB
LDWI 0AH
STWR RB
SLEEP

FAIL_RBIN: CLRW
CPIO RB
LDWI 0BH
STWR RB
SLEEP







; ----- STAGE2 RAM testing ---------------------------------------------------------------------------------
STAGE2: CLRW
CPIO RA
CPIO RB

INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

LDWI 11000000B
STWR 07H
STWR TEMP0
LDWI 07H
STWR MSR
LDR INDR_ADD,W
XORWR TEMP0,W
BTSS STATUS,Z
LJUMP RAMFAIL

LDWI 0DH ; Initial address 0DH
STWR MSR ; MSR point
STWR TEMP0 ; "0CH" Compare value
LDWI 080H ; Make compare value to match real saving value
ADDWR TEMP0,1 ; "EDH"
LCALL SHOWADD
BANK0: LDR MSR,W ; Load the address where MSR point to
STWR INDR_ADD ; Save address value to itself
LDR TEMP0,W
XORWR INDR_ADD,W
BTSS STATUS,Z
LJUMP RAMFAIL
LDR MSR,W
STWR RB
COMR RB,1
LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
INCR TEMP0,1 ; compare value +1
XORWI 09FH
BTSS STATUS,Z
LJUMP BANK0

LDWI 30H ; Initial address 30H
STWR MSR ; MSR point
STWR TEMP0 ; "30H" Compare value
LDWI 80H ; Make compare value to match real saving value
ADDWR TEMP0,1 ; "B0H"
BANK123: LDR MSR,W ; Load the address where MSR point to
STWR INDR_ADD ; Save address value to itself
LDR TEMP0,W
XORWR INDR_ADD,W
BTSS STATUS,Z
LJUMP RAMFAIL
LDR MSR,W
STWR RB
COMR RB,1
LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
BSR MSR,4
INCR TEMP0,1 ; compare value +1
BSR TEMP0,4
XORWI 0FFH
BTSS STATUS,Z
LJUMP BANK123

LDR RB,W
STWR TEMP0
COMR TEMP0,1
COMR RB,1
LCALL DELAY
LCALL SHOWADD

CLRWT
INCR STAGE,W
STWR RA
STWR RB

COMR RA,1
COMR RB,1

SLEEP

RAMFAIL: LDR MSR,W
STWR RB
COMR RB,1
SLEEP

SHOWADD: LDWI 03H
STWR TEMP1
RESHOW: LDR TEMP0,W
STWR RB
COMR RB,1
LCALL DELAY
LDWI 0FFH
STWR RB
LCALL DELAY
DECRSZ TEMP1
LJUMP RESHOW
RTIW 00H


; ----- STAGE4 WDT testing --------------------------------------------------------------------------------
STAGE4: CLRW
CPIO RA
CPIO RB

INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

BEGIN1: CLRWT ; Set initial value
CLRR TEMP2 ; Set PC ++ register
LDWI 08H ; Set testing cycle count
STWR TEMP3
LDWI 00001000B ; Set WDT RATE 1
TMODE
LCALL HIBYTE ; RB Hi-byte light on
LDWI 01H ; RA shows 1
STWR RA
COMR RA,1
LJUMP DUMMY ; Dummy for WDT testing & Set 10H.11H.12H to save count value

BEGIN1A: CLRWT
DECRSZ TEMP3,1 ; Check tesing cycle
LJUMP BEGIN2 ; Countinue testing
CLRWT
LJUMP WDTEND ; Cycle finish to end stage4


BEGIN2: CLRWT
LDR TEMP2,W
ADDWR PC,1
LJUMP R2
LJUMP R4
LJUMP R8
LJUMP R16
LJUMP R32
LJUMP R64
LJUMP R128
LJUMP WDTEND

R2: LDWI 00001001B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 02H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R4: LDWI 00001010B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 03H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R8: LDWI 00001011B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 04H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R16: LDWI 00001100B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 05H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R32: LDWI 00001101B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 06H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R64: LDWI 00001110B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 07H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R128: LDWI 00001111B
TMODE
CLRW
CPIO RA
CPIO RB

SWAPR RB

LDWI 08H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

WDTEND: CLRWT
CLRW
CPIO RA
CPIO RB

INCR STAGE,W
STWR RA
STWR RB

COMR RA,1
COMR RB,1

SLEEP


DUMMY: CLRR 10H
CLRR 11H
CLRR 12H
CLRR 13H
CLRR 14H
CLRR 15H
CLRR 16H
CLRR 17H
CLRWT
B0: INCRSZ 17H ; 1 * 256 * ( 255 * 255 )
LJUMP B0 ; 2 * 255 * ( 255 * 255 )
B1: INCRSZ 16H ; 1 * 256 * 255
LJUMP B0 ; 2 * 255 * 255
B2: INCRSZ 15H ; 1 * 256
LJUMP B0 ; 2 * 255
SLEEP

HIBYTE: LDWI 11110000B
STWR RB

COMR RB,1

RET

; ----- STAGE3 RTCC testing --------------------------------------------------------------------------------
STAGE3: CLRW
CPIO RA
CPIO RB

INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

CLRR RTCC

LDWI 00111000B ; set 1_external rtcc 2_hi to lo edge 3_not assign rtcc 4_no rate
TMODE

EXTERHI: CLRWT
LDR RTCC,W ; push bottom 0~7 by Hi to Lo trigger
STWR TEMP2
COMR TEMP2,W
STWR RA
STWR RB
LDWI 00000111B
SUBWR RTCC,W
BTSS STATUS,Z
LJUMP EXTERHI

LDWI 00101000B ; set 1_external rtcc 2_lo to hi edge 3_not assign rtcc 4_no rate
TMODE

EXTERLO: CLRWT
LDR RTCC,W ; push bottom 8~F by Lo to Hi trigger
STWR TEMP2
COMR TEMP2,W
STWR RA
STWR RB
LDWI 00001111B
SUBWR RTCC,W
BTSS STATUS,Z
LJUMP EXTERLO

LDWI 0FFH
STWR RA
STWR RB
BSR STATUS,C
BCR RA,0
BCR RB,0

LDWI 00000111B ; 1:256
TMODE
LCALL RTCCSET

LDWI 00000110B ; 1:128
TMODE
LCALL RTCCSET

LDWI 00000101B ; 1: 64
TMODE
LCALL RTCCSET

LDWI 00000100B ; 1: 32
TMODE
LCALL RTCCSET

LDWI 00000011B ; 1: 16
TMODE
LCALL RTCCSET

LDWI 00000010B ; 1: 8
TMODE
LCALL RTCCSET

LDWI 00000001B ; 1: 4
TMODE
LCALL RTCCSET

LDWI 00000000B ; 1: 2
TMODE
LCALL RTCCSET


CLRR RTCC
LDWI 00000111B ; 1:256
TMODE
CLRWT
LDWI 00001111B
TMODE

CLRWT
INCR STAGE,W
STWR RA
STWR RB

COMR RA,1
COMR RB,1

SLEEP

RTCCSET: CLRR RTCC ; wait delayck time 143.2 uS to check rtcc value
LCALL DELAYCK ; freq. 10 MHz , RTCC timer = 10/4 =2.5 MHz
LDR RTCC,W
LCALL DELAYRT ; dummy delay
BSR STATUS,C
RLR RA,1
BSR STATUS,C
RLR RB,1
RTIW 00H



DELAYCK: LDWI 007H ; * 1 = 1 = 1 1: 2 = 143.2 / 0.8 = 179 ~ 179 D = B3 H
STWR DELAY_1 ; * 1 = 1 = 1 1: 4 = 143.2 / 1.6 = 89.5 ~ 90 D = 5A H
; 1: 8 = 143.2 / 3.2 = 44.75 ~ 45 D = 2D H
DELAYCK1: LDWI 010H ; * 7 = 7 = 7 1: 16 = 143.2 / 6.4 = 22.375 ~ 22 D = 15 H
STWR DELAY_2 ; * 7 = 7 = 7 1: 32 = 143.2 / 12.8 = 11.1875 ~ 11 D = 0B H
DELAYCK2: CLRWT
DECRSZ DELAY_2 ; * 16 * 7 = 112 = 112 1: 64 = 143.2 / 25.6 = 5.59375 ~ 6 D = 06 H
LJUMP DELAYCK2 ; * 15 * 7 = 105 * 2 = 210 1: 128 = 143.2 / 51.2 = 2.796875 ~ 3 D = 03 H
; 1: 256 = 143.2 / 102.4 = 1.3984375 ~ 1 D = 01 H
DECRSZ DELAY_1 ; * 7 = 7 = 7
LJUMP DELAYCK1 ; * 6 = 6 * 2 = 12
RTIW 00H ; * 1 = 1 = 1 TOTAL = 358 instruction time / 358 * 0.4uS = 143.2uS



DELAYRT: STWR DELAY_1 ;

DELAYRT1: LDWI 01FH ;
STWR DELAY_2 ;

DELAYRT2: CLRWT
LDWI 0FFH ;
STWR TEMP3 ;

DELAYRT3: CLRWT
DECRSZ TEMP3 ;
LJUMP DELAYRT3 ;

DECRSZ DELAY_2 ;
LJUMP DELAYRT2 ;

DECRSZ DELAY_1 ;
LJUMP DELAYRT1 ;

RTIW 00H ;



; ===== COMMON SUB-PROGRAM BLOCK ===========================================================================
DELAY: CLRWT ;*1
LDWI 0FFH ;*1
STWR DELAY_1 ;*1

DELAY1: LDWI 0FFH ;*256
STWR DELAY_2 ;*256
DELAY2: CLRWT ;*256*256
DECRSZ DELAY_2 ;*256*256
LJUMP DELAY2 ;*255*256

DECRSZ DELAY_1 ;*256
LJUMP DELAY1 ;*255
RET ;*1

TRIPLE: LDWI 03H
STWR TEMP0
TWICELP: LDR TEMP1,W
STWR RA
COMR RA,1
STWR RB
COMR RB,1


LCALL DELAY
LDWI 0FFH
STWR RA
STWR RB

LCALL DELAY
DECRSZ TEMP0,1
LJUMP TWICELP
RET


ORG 1FFH
LJUMP BEGIN
ORG 3FFH
LJUMP BEGIN
ORG 7FFH
LJUMP BEGIN

END