DEMO PROGRAM MDT10P73

; ===== DESCRIPTION ========================================================================================
; for IMD103 7X series: 10P73

; ===== REGISTER DEFINITION (RAM MAPPING) ==================================================================


; --- PAGE 0 -----------------------------------------------------------------------------------------------
INDF EQU 00H ;00H
TMR0 EQU 01H ;01H
PCL EQU 02H ;02H
STATUS EQU 03H ;03H
MSR EQU 04H ;04H
RA EQU 05H ;05H
RB EQU 06H ;06H
RC EQU 07H ;07H
RD EQU 08H ;08H
RE EQU 09H ;09H
PCH EQU 0AH ;0AH
INTS EQU 0BH ;0BH
PIFB1 EQU 0CH ;0CH
PIFB2 EQU 0DH ;0DH
TMR1L EQU 0EH ;0EH
TMR1H EQU 0FH ;0FH
T1STA EQU 10H ;10H
TMR2 EQU 11H ;11H
T2STA EQU 12H ;12H
SCMBUF EQU 13H ;13H
SCMCTL EQU 14H ;14H
CCP1L EQU 15H ;15H
CCP1H EQU 16H ;16H
CCP1CTL EQU 17H ;17H
RCSC EQU 18H ;18H
TXREG EQU 19H ;19H
RCREG EQU 1AH ;1AH
CCP2L EQU 1BH ;1BH
CCP2H EQU 1CH ;1CH
CCP2CTL EQU 1DH ;1DH
ADRES EQU 1EH ;1EH
ADS0 EQU 1FH ;1FH

DELAY_1 EQU 20H ;20H
DELAY_2 EQU 21H ;21H
STAGE EQU 22H ;22H
STAGELP EQU 23H ;23H
STAGE3T EQU 24H ;24H
TEMP0 EQU 25H ;25H
TEMP1 EQU 26H ;26H
TEMP2 EQU 27H ;27H
TEMP3 EQU 28H ;28H
TEMP4 EQU 29H ;29H
TEMP5 EQU 2AH ;2AH
TEMP6 EQU 2BH ;2BH

; --- PAGE 1 -----------------------------------------------------------------------------------------------
;80H
OPTION EQU 81H ;81H
;82H
;83H
;84H
CPIOA EQU 85H ;85H
CPIOB EQU 86H ;86H
CPIOC EQU 87H ;87H
CPIOD EQU 88H ;88H
CPIOE EQU 89H ;89H
;8AH
;8BH
PIEB1 EQU 8CH ;8CH
PIEB2 EQU 8DH ;8DH
PSTA EQU 8EH ;8EH
;8FH
;90H
;91H
T2PER EQU 92H ;92H
;93H
SCMSTA EQU 94H ;94H
;95H
;96H
;97H
TXSC EQU 98H ;98H
BRREG EQU 99H ;99H
;9AH
;9BH
;9CH
;9DH
;9EH
ADS1 EQU 9FH ;9FH

; ===== STATUS DEFINITION ==================================================================================
C EQU 0
HC EQU 1
Z EQU 2
PF EQU 3
TF EQU 4
RBS0 EQU 5
ADIF EQU 6
CCP1IF EQU 2

; ===== OTHERS DEFINITION ==================================================================================
W EQU 0
PRDB EQU 0
PORB EQU 1

; ===== MAIN-PROGRAM BLOCK =================================================================================
; ----- 檢查 STATUS 暫存器的 B4(TF) 及 B3(PF), 依 RESET 原因作 DEMO 程式的流程控制 -------------------------
;if TF為是'0': PF為是'0'> 代表 IC 進入 sleep 後被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以進行跳關
; : PF為否'1'> 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至指定的副程式作 WDT 功能檢測
;if TF為否'1': PF為是'0'> 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序
; : PF為否'1'> Power on reset 或程式進行中作 MCLR reset


; ----- RESET VECTOR ---------------------------------------------------------------------------------------
ORG 00H ; 以下程式碼由 00H 的位址開始存入程式記憶體(ROM)
LJUMP BEGIN

; ----- INTERRUPT VECTOR -----------------------------------------------------------------------------------
ORG 04H
CLRWT
LCALL SET_PAGE0

BCR T1STA,0 ; Stop TMR1

BTSC PIFB1,6 ; ADIF
LJUMP INTAD2

BTSC INTS,2
LJUMP INTTMR0

BTSC PIFB1,2 ; CCP1IF
LJUMP INTCCP

BTSC PIFB2,0 ; CCP2IF
LJUMP INTCCP
;
; BTSC INTS,1
; LJUMP INTEXTPB0
;
; BTSC INTS,2
; LJUMP INTTMR0

RTFI


ORG 10H
BEGIN: LCALL SET_PAGE1
LDWI 00000111B ; Set PA3~PA0 in digital I/O mode
STWR ADS1
LCALL SET_PAGE0
BTSS STATUS,TF ; check TF 判斷是否被 WDT reset, 0:是 1:否
LJUMP TF0 ; TF=0, IC 被 WDT reset, 跳至 'TF0 副程式'

TF1: BTSS STATUS,PF ; TF=1, IC 未被 WDT reset, check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP PF0 ; ____PF=0, 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序

LJUMP STAGE1 ; ____PF=1, Power on reset, 跳至 'STAGE1 副程式'


TF0: LCALL SETRA_OUT ; 因為 TF=0, IC 被 WDT reset
BTSC STATUS,PF ; check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP TF0PF1 ; ____PF=1, 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至 'TF0PF1 副程式' 進行 WDT test
LCALL SETRB_OUT
SLEEP ; ____PF=0, 代表 IC 進入 sleep 後又被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以跳至 'PF0 副程式',
LJUMP BEGIN ; 並以 STAGE 暫存器之累加值進行關卡轉換

TF0PF1: CLRWT
LJUMP BEGIN1A ; 跳至 'BEGIN1A 副程式' 進行 WDT test


PF0: LDWI 11110000B
ANDWR CCP1CTL,1
ANDWR CCP2CTL,1
LDR STAGE,W ; 將 STAGE 暫存器累加值與目前 PC 值相加
ADDWR PCL,1 ; 相加後的 PC 值指向欲測試之關卡
LJUMP STAGE2 ; RAM testing
LJUMP STAGE3 ; TMR0 testing
LJUMP STAGE4 ; WDT testing
LJUMP STAGE5 ; A/D interrupt
LJUMP STAGE6 ; Capture_TMR1 testing
LJUMP STAGE7 ; Compare_TMR1 testing
LJUMP STAGE8 ; PWM_____TMR2 testing
LJUMP STAGE1 ; I/O testing

; ----- STAGE1 I/O testing ---------------------------------------------------------------------------------
STAGE1: LCALL SET_PAGE0
LDWI 10101010B
STWR RA
STWR RB
STWR RC
STWR RD
STWR RE

TESTIN_BI: XORWR RB,1
BTSC STATUS,Z
LJUMP FAILRBIN
TESTIN_CI: XORWR RC,1
BTSC STATUS,Z
LJUMP FAILRCIN
;TESTIN_DI: XORWR RD,1
; BTSC STATUS,Z
; LJUMP FAILRDIN

TESTIN_AI: LDWI 00101010B
XORWR RA,1
BTSC STATUS,Z
LJUMP FAILRAIN

;TESTIN_EI: LDWI 00000010B
; XORWR RE,1
; BTSC STATUS,Z
; LJUMP FAILREIN

LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
; LCALL SETRD_OUT
; LCALL SETRE_OUT

;.............................
TESTIN_BO: LDWI 01010101B
XORWR RB,1
BTSS STATUS,Z
LJUMP FAILRBIN
COMR RB,1

TESTIN_CO: XORWR RC,1
BTSS STATUS,Z
LJUMP FAILRCIN
COMR RC,1

;TESTIN_DO: XORWR RD,1
; BTSS STATUS,Z
; LJUMP FAILRDIN
; COMR RD,1

TESTIN_AO: LDWI 00010101B
XORWR RA,1
BTSS STATUS,Z
LJUMP FAILRAIN
LDWI 0FFH
STWR RA

;TESTIN_EO: LDWI 00000101B
; XORWR RE,1
; BTSS STATUS,Z
; LJUMP FAILREIN
; COMR RE,1

;.............................
CLRR STAGE
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

;.............................
CLRR TEMP0
ADDRA: CLRWT
LDR TEMP0,W
ADDWR PCL,1
LJUMP RA01H
LJUMP RA03H
LJUMP RA07H
LJUMP RA0FH
LJUMP RA1FH
LJUMP RA3FH
LJUMP IOEND

OUTTEST: CLRR RB
CLRR RC
CLRR RD
CLRR RE
BSR STATUS,C
LOOPRB: CLRWT
RRR RB
LCALL DELAY
BTSS STATUS,C
LJUMP LOOPRB
LOOPRC: CLRWT
RRR RC
LCALL DELAY
BTSS STATUS,C
LJUMP LOOPRC
;LOOPRD: CLRWT
; RRR RD
; LCALL DELAY
; BTSS STATUS,C
; LJUMP LOOPRD

; BCR STATUS,C
; BSR RE,2
; LCALL DELAY
;LOOPRE: CLRWT
; RRR RE
; BCR RE,2
; LCALL DELAY
; BTSS STATUS,C
; LJUMP LOOPRE

INCR TEMP0
LJUMP ADDRA

RA01H: LDWI 11111110B
STWR RA
LJUMP OUTTEST

RA03H: LDWI 11111100B
STWR RA
LJUMP OUTTEST

RA07H: LDWI 11111000B
STWR RA
LJUMP OUTTEST

RA0FH: LDWI 11110000B
STWR RA
LJUMP OUTTEST

RA1FH: LDWI 11100000B
STWR RA
LJUMP OUTTEST

RA3FH: LDWI 11000000B
STWR RA
LJUMP OUTTEST

IOEND: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RA
STWR RC
STWR RD
STWR RE
SLEEP
LJUMP BEGIN

;.............................
FAILRAIN: LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 11111110B
STWR RC
LDWI 0FFH
STWR RA
STWR RD
STWR RE
SLEEP
LJUMP BEGIN

FAILRBIN: LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 11111101B
STWR RC
LDWI 0FFH
STWR RA
STWR RD
STWR RE
SLEEP
LJUMP BEGIN

FAILRCIN: LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 11111100B
STWR RC
LDWI 0FFH
STWR RA
STWR RD
STWR RE
SLEEP
LJUMP BEGIN

;FAILRDIN: LDR STAGE3T,W
; STWR RB
; COMR RB,1
; LDWI 11111011B
; STWR RC
; LDWI 0FFH
; STWR RA
; STWR RD
; STWR RE
; SLEEP
; LJUMP BEGIN

;FAILREIN: LDR STAGE3T,W
; STWR RB
; COMR RB,1
; LDWI 11111010B
; STWR RC
; LDWI 0FFH
; STWR RA
; STWR RD
; STWR RE
; SLEEP
; LJUMP BEGIN

; ----- STAGE2 RAM testing ---------------------------------------------------------------------------------
STAGE2: LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_OUT

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

LDWI 28H ; Initial address 28H
STWR MSR ; MSR point
STWR TEMP0 ; "10H" Compare value
STWR TEMP1
LCALL TRIRC
BANK0: LDR MSR,W ; Load the address where MSR point to
STWR INDF ; Save address value to itself
LDR TEMP0,W
XORWR INDF,W
BTSS STATUS,Z
LJUMP RAMFAIL
LDR MSR,W
STWR RC
COMR RC,1
LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
INCR TEMP0,1 ; compare value +1
XORWI 07FH
BTSS STATUS,Z
LJUMP BANK0

LDWI 01H
STWR RB
COMR RB,1

LDWI 0A0H ; Initial address A0H
STWR MSR ; MSR point
STWR TEMP0 ; "10H" Compare value
STWR TEMP1
LCALL TRIRC
BANK1: LDR MSR,W ; Load the address where MSR point to
STWR INDF ; Save address value to itself
LDR TEMP0,W
XORWR INDF,W
BTSS STATUS,Z
LJUMP RAMFAIL
LDR MSR,W
STWR RC
COMR RC,1
LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
INCR TEMP0,1 ; compare value +1
XORWI 0FFH
BTSS STATUS,Z
LJUMP BANK1

DECR TEMP0,W
STWR TEMP1
LCALL TRIRC

RAMEND: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN

RAMFAIL: LDR MSR,W
STWR RC
COMR RC,1
SLEEP
LJUMP BEGIN

; ----- STAGE3 TMR0 testing --------------------------------------------------------------------------------
STAGE3: LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_OUT

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

CLRR TMR0

LCALL SET_PAGE1
LDWI 00111000B ; set 1_external TMR0 2_hi to lo edge 3_not assign TMR0 4_no rate
TMODE

LCALL SET_PAGE0

EXTERHI: CLRWT
LDR TMR0,W ; push bottom 0~7 by Hi to Lo trigger
STWR TEMP0
COMR TEMP0,W
STWR RC
LDWI 00000111B
SUBWR TMR0,W
BTSS STATUS,Z
LJUMP EXTERHI

LDWI 00101000B ; set 1_external TMR0 2_lo to hi edge 3_not assign TMR0 4_no rate
TMODE

EXTERLO: CLRWT
LDR TMR0,W ; push bottom 8~F by Lo to Hi trigger
STWR TEMP0
COMR TEMP0,W
STWR RC
LDWI 00001111B
SUBWR TMR0,W
BTSS STATUS,Z
LJUMP EXTERLO

LDWI 11000000B
STWR INTS

LDWI 0FFH
STWR RB
STWR RC
BSR STATUS,C
BCR RB,0

LDWI 00000000B ; 1: 2
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000001B ; 1: 4
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000010B ; 1: 8
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000011B ; 1: 16
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000100B ; 1: 32
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000101B ; 1: 64
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000110B ; 1:128
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

BCR INTS,2
LDWI 00000111B ; 1:256
TMODE
CLRR TMR0
BSR INTS,5
CLRR TEMP0
CLRR TEMP1
CLRR TEMP2
LCALL TMR0DMY

CLRR TMR0
CLRWT
LDWI 00001111B
TMODE

TMR0END: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN

TMR0DMY: CLRWT
INCR TEMP2,1
BTSC INTS,2
RET
LDWI 0FFH
XORWR TEMP2,W
BTSS STATUS,Z
LJUMP CHKTMR0FG
INCR TEMP1,1
LDWI 0FFH
XORWR TEMP1,W
BTSS STATUS,Z
LJUMP CHKTMR0FG
INCR TEMP0,1
LDWI 0FFH
XORWR TEMP0,W
BTSS STATUS,Z
LJUMP CHKTMR0FG
CHKTMR0FG: BTSC INTS,2
RET
LJUMP TMR0DMY

;...........TMR0 overflow interrupt sub-program...............
INTTMR0: CLRR TEMP3
CLRR TEMP4
CLRR TEMP5
CLRR TEMP6

CHKTEMP0: LDR TEMP0,W
XORWR TEMP3,W
BTSS STATUS,Z
LJUMP ADDTEMP6B2
LJUMP CHKTEMP1

CHKTEMP1: LDR TEMP1,W
XORWR TEMP4,W
BTSS STATUS,Z
LJUMP ADDTEMP6B1
LJUMP CHKTEMP2

CHKTEMP2: LDR TEMP2,W
XORWR TEMP5,W
BTSS STATUS,Z
LJUMP ADDTEMP6B0
LJUMP INTTMR0FSH

ADDTEMP6B2: CLRWT
INCRSZ TEMP6,1
LJUMP ADDTEMP6B2
INCRSZ TEMP5,1
LJUMP ADDTEMP6B2
INCRSZ TEMP4,1
LJUMP ADDTEMP6B2
INCR TEMP3,1
LDR TEMP0,W
XORWR TEMP3,W
BTSS STATUS,Z
LJUMP ADDTEMP6B2

ADDTEMP6B1: CLRWT
INCRSZ TEMP6,1
LJUMP ADDTEMP6B1
INCRSZ TEMP5,1
LJUMP ADDTEMP6B1
INCR TEMP4,1
LDR TEMP1,W
XORWR TEMP4,W
BTSS STATUS,Z
LJUMP ADDTEMP6B1

ADDTEMP6B0: CLRWT
INCRSZ TEMP6,1
LJUMP ADDTEMP6B0
INCR TEMP5,1
LDR TEMP2,W
XORWR TEMP5,W
BTSS STATUS,Z
LJUMP ADDTEMP6B0

INTTMR0FSH: RLR RB,1
BCR INTS,5
CLRR TMR0
CLRR TEMP0
CLRR TEMP1
RTFI




; ----- STAGE4 WDT testing --------------------------------------------------------------------------------
STAGE4: LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_OUT

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

BEGIN1: CLRWT ; Set initial value
CLRR TEMP0 ; Set PC ++ register
LDWI 08H ; Set testing cycle count
STWR TEMP1
LDWI 00001000B ; Set WDT RATE 1
TMODE
LCALL RCHI ; RB Hi-byte light on
LDWI 01H ; RA shows 1
STWR RB
COMR RB,1
LJUMP DUMMY ; Dummy for WDT testing & Set 10H.11H.12H to save count value

BEGIN1A: CLRWT
LCALL SETRB_OUT
LCALL SETRC_OUT
DECRSZ TEMP1,1 ; Check tesing cycle
LJUMP BEGIN2 ; Countinue testing
CLRWT
LJUMP WDTEND ; Cycle finish to end stage4


BEGIN2: CLRWT
LDWI 01H
STWR PCH
LDR TEMP0,W
ADDWR PCL,1
LJUMP R2
LJUMP R4
LJUMP R8
LJUMP R16
LJUMP R32
LJUMP R64
LJUMP R128
LJUMP WDTEND

R2: LDWI 00001001B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 02H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

R4: LDWI 00001010B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 03H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

R8: LDWI 00001011B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 04H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

R16: LDWI 00001100B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 05H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

R32: LDWI 00001101B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 06H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

R64: LDWI 00001110B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 07H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

R128: LDWI 00001111B
TMODE
LCALL SETRB_OUT
LCALL SETRC_OUT
SWAPR RC
LDWI 08H
STWR RB
COMR RB,1
INCR TEMP0,1
LJUMP DUMMY

WDTEND: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN


DUMMY: CLRR 28H
CLRR 29H
CLRR 2AH
CLRR 2BH
CLRR 2CH
CLRR 2DH
CLRR 2EH
CLRR 2FH
CLRWT
B0: INCRSZ 2FH ; 1 * 256 * ( 255 * 255 )
LJUMP B0 ; 2 * 255 * ( 255 * 255 )
B1: INCRSZ 2EH ; 1 * 256 * 255
LJUMP B0 ; 2 * 255 * 255
B2: INCRSZ 2DH ; 1 * 256
LJUMP B0 ; 2 * 255
SLEEP
LJUMP BEGIN

RCHI: LDWI 11110000B
STWR RC
COMR RC,1
RET

; ----- STAGE 5. A/D conversion test (R08.R09.R0B.R88) Vref=PA3 --------------------------------------------
; 利用 A/D INT flag 作檢查
; 將ADS1設為01H
; Vref=PA3 , A/D ch are PA2 . PA1 . PA0
; Pass message RA = 04H / RB =66H

STAGE5: LCALL SET_PAGE1
LDWI 00000000B
STWR ADS1
LCALL SETRA_IN
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_IN

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

CLRWT
LDWI 00111111B
TMODE

CLRR TMR0

LDWI 11000000B ; Set total INT on, turn off all source except A/D & clear all flag
STWR INTS
LCALL SET_PAGE1
LDWI 01000000B ; A/D interrupt enable
STWR PIEB1

LCALL SET_PAGE0 ; Select page 0
CLRR ADRES

WAITINTF: CLRWT

LDWI 00H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP ADCH0

LDWI 01H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP ADCH1

LDWI 02H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP ADCH2

LDWI 03H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP ADCH3

LDWI 04H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP ADCH4

; LDWI 05H
; XORWR TMR0,W
; BTSC STATUS,Z
; LJUMP ADCH5

; LDWI 06H
; XORWR TMR0,W
; BTSC STATUS,Z
; LJUMP ADCH6

; LDWI 07H
; XORWR TMR0,W
; BTSC STATUS,Z
; LJUMP ADCH7

LJUMP STAGE5_FSH

WAITINTB: LJUMP WAITINTF

ADCH0: LDWI 01000101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
STWR ADS0
LJUMP WAITINTB

ADCH1: LDWI 01001101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
STWR ADS0
LJUMP WAITINTB

ADCH2: LDWI 01010101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
STWR ADS0
LJUMP WAITINTB

ADCH3: LDWI 01011101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
STWR ADS0
LJUMP WAITINTB

ADCH4: LDWI 01100101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
STWR ADS0
LJUMP WAITINTB

;ADCH5: LDWI 01101101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
; STWR ADS0
; LJUMP WAITINTB

;ADCH6: LDWI 01110101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
; STWR ADS0
; LJUMP WAITINTB

;ADCH7: LDWI 01111101B ; Set conversion timing use RC,A/D module turn on standby & clear A/D INT flag
; STWR ADS0
; LJUMP WAITINTB

STAGE5_FSH: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN

INTAD2: CLRWT
LCALL SET_PAGE0 ; Select page 0
LDR ADRES,W
STWR TEMP1
COMR TEMP1,W
STWR RC
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
BCR PIFB1,ADIF ; Clear A/D flag
RTFI


; ----- STAGE6 Capture_TMR1 testing ------------------------------------------------------------------------
STAGE6: LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_OUT

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

INCR STAGE,W
STWR RB
COMR RB,1


LCALL SET_PAGE1
BSR CPIOC,1
BSR CPIOC,2

LCALL SET_PAGE0
CLRWT
LDWI 00111111B
TMODE

LDWI 11000000B ; Set total INT on, turn off all interrupt
STWR INTS
LDWI 00000000B ; Clear all interrupt flag
STWR PIFB1

LCALL SET_PAGE1 ; Turn off all interrupt except CCPIE enable
LDWI 00000100B
STWR PIEB1
LDWI 00000001B
STWR PIEB2

LCALL SET_PAGE0
LDWI 00000000B ; Prescaler rate 1:1 ; TMR1 Osc off ; Synchronize enable ; select internal clk(Fosc/4) ; stop TMR1
STWR T1STA

CLRR TMR0
CLRR TMR1L
CLRR TMR1H


CCP1LOOP: CLRWT

LDWI 00H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP1LOOP

LDWI 01H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP1FALL

LDWI 02H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP1RISE

LDWI 03H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP1X4

LDWI 04H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP1X16

LDWI 05H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP2FALL

LDWI 06H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP2RISE

LDWI 07H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP2X4

LDWI 08H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP CCP2X16

LJUMP STAGE6_FSH

CCP1COMP: CLRWT
LCALL SET_PAGE0
BSR T1STA,0 ; Enable TMR1
COMR TEMP0,W
STWR RB
LDR TMR0,W
XORWR TEMP0,W
BTSC STATUS,Z
LJUMP CCP1COMP
CLRW
STWR CCP1CTL ; Turn off CCP1 function
STWR CCP2CTL ; Turn off CCP2 function
LJUMP CCP1LOOP

CCP1FALL: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000100B ; Capture1 mode, every falling edge
STWR CCP1CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP1RISE: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000101B ; Capture1 mode, every rising edge
STWR CCP1CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP1X4: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000110B ; Capture1 mode, every 4th rising edge
STWR CCP1CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP1X16: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000111B ; Capture1 mode, every 16th rising edge
STWR CCP1CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP2FALL: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000100B ; Capture1 mode, every falling edge
STWR CCP2CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP2RISE: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000101B ; Capture1 mode, every rising edge
STWR CCP2CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP2X4: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000110B ; Capture1 mode, every 4th rising edge
STWR CCP2CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP

CCP2X16: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00000111B ; Capture1 mode, every 16th rising edge
STWR CCP2CTL
LCALL SET_PAGE0
CLRR CCP1L
CLRR CCP1H
CLRR CCP2L
CLRR CCP2H
LJUMP CCP1COMP



STAGE6_FSH: LCALL SET_PAGE1
BCR PIEB1,2
CLRWT
LCALL SET_PAGE0
LDWI 00000000B ; Prescaler rate 1:1 ; TMR Osc off ; Synchronize enable ; select internal ; stop TMR1
STWR T1STA
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN

INTCCP: LCALL SET_PAGE1
LDWI 00000110B
ANDWR CPIOC,W
XORWI 00000110B
BTSS STATUS,Z
LJUMP INTCPR ; Go to Compare testing

LCALL SET_PAGE0

LDWI 0FFH
STWR TEMP1
LCALL TRIRB

BCR PIFB1,2 ; Clear CCP1IF
BCR PIFB2,0 ; Clear CCP2IF
CLRR TMR1L
CLRR TMR1H
RTFI


; ----- STAGE7 Compare_TMR1 testing ------------------------------------------------------------------------
STAGE7: LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_OUT

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

INCR STAGE,W
STWR RB
COMR RB,1

LCALL SET_PAGE0
CLRWT
LDWI 00111111B
TMODE

LDWI 11000000B ; Set total INT on, turn off all interrupt
STWR INTS
LDWI 00000000B ; Clear all interrupt flag
STWR PIFB1

LCALL SET_PAGE1 ; Turn off all interrupt except CCPIE enable
LDWI 00000100B
STWR PIEB1
LDWI 00000001B
STWR PIEB2

LCALL SET_PAGE0
LDWI 00110000B ; Prescaler rate 1:1 ; TMR1 Osc off ; Synchronize enable ; select internal clk(Fosc/4) ; stop TMR1
STWR T1STA

CLRR TMR0
CLRR TMR1L
CLRR TMR1H

LDWI 0FFH
STWR CCP1L
STWR CCP1H
STWR CCP2L
STWR CCP2H


BSR RC,2 ; CCP1 output Hi : LED turns off
BSR RC,1 ; CCP2 output Hi : LED turns off
; PC2(CCP1)/PC1(CCP2) : 1/1

LCALL SET_PAGE0

CLRR TEMP0
CPR1: LDWI 00001010B ; CCP1 HAVE NO CHANGE ON PIN(PC2) ON PIN
STWR CCP1CTL
LDWI 00001001B ; CCP2 OUTPUT LO ON PIN(PC1) WHEN CCP2 INT OCCURS
STWR CCP2CTL ; PC2(CCP1)/PC1(CCP2) : 1/0
BSR T1STA,0
DUMMYCPR1: CLRWT
LDWI 66H ; Check backing flag TEMP0=66 leave from INT
XORWR TEMP0,W
BTSS STATUS,Z
LJUMP DUMMYCPR1

CLRR TEMP0
CPR2: LDWI 00001001B ; CCP1 OUTPUT LO ON PIN(PC2)WHEN CCP1 INT OCCURS
STWR CCP1CTL
LDWI 00001000B ; CCP2 OUTPUT HI ON PIN(PC1)WHEN CCP2 INT OCCURS
STWR CCP2CTL ; PC2(CCP1)/PC1(CCP2) : 0/1
BSR T1STA,0
DUMMYCPR2: CLRWT
LDWI 66H ; Check backing flag TEMP0=66 leave from INT
XORWR TEMP0,W
BTSS STATUS,Z
LJUMP DUMMYCPR2

CLRR TEMP0
CPR3: LDWI 00001001B ; CCP1 OUTPUT LO ON PIN(PC2)WHEN CCP1 INT OCCURS
STWR CCP1CTL
LDWI 00001001B ; CCP2 OUTPUT LO ON PIN(PC1)WHEN CCP2 INT OCCURS
STWR CCP2CTL ; PC2(CCP1)/PC1(CCP2) : 0/0
BSR T1STA,0
DUMMYCPR3: CLRWT
LDWI 66H ; Check backing flag TEMP0=66 leave from INT
XORWR TEMP0,W
BTSS STATUS,Z
LJUMP DUMMYCPR3

BCR RC,2 ; CCP1 output Hi : LED turns on
BCR RC,1 ; CCP2 output Hi : LED turns on
; PC2(CCP1)/PC1(CCP2) : 0/0

CLRR TEMP0
CPR4: LDWI 00001010B ; CCP1 HAVE NO CHANGE ON PIN(PC2) ON PIN
STWR CCP1CTL
LDWI 00001010B ; CCP1 HAVE NO CHANGE ON PIN(PC2) ON PIN
STWR CCP2CTL ; PC2(CCP1)/PC1(CCP2) : 0/0
BSR T1STA,0
DUMMYCPR4: CLRWT
LDWI 66H ; Check backing flag TEMP0=66 leave from INT
XORWR TEMP0,W
BTSS STATUS,Z
LJUMP DUMMYCPR4

LDWI 0FFH
STWR RC

STAGE7_FSH: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN

INTCPR: LCALL SET_PAGE0

LDWI 08H
STWR TEMP1
RESWTEMP1: LCALL DELAY
DECRSZ TEMP1
LJUMP RESWTEMP1

CLRR CCP1CTL
CLRR CCP2CTL
CLRR TMR1L
CLRR TMR1H
BCR PIFB1,2
BCR PIFB2,0
LDWI 66H
STWR TEMP0
RTFI


; ----- STAGE8 PWM_____TMR2 testing ------------------------------------------------------------------------
STAGE8: LCALL SETRA_OUT
LCALL SETRB_OUT
LCALL SETRC_OUT
LCALL SETRD_OUT
LCALL SETRE_OUT

LCALL SET_PAGE0

INCR STAGE,1
INCR STAGE,W
STWR STAGE3T
LCALL TRIPLE

INCR STAGE,W
STWR RB
COMR RB,1

LCALL SET_PAGE0
CLRWT
LDWI 00111111B
TMODE

LDWI 00000000B ; Set total INT off, turn off all interrupt
STWR INTS
LDWI 00000000B ; Clear all interrupt flag
STWR PIFB1

LCALL SET_PAGE1 ; Turn off all interrupt
LDWI 00000000B
STWR PIEB1
LDWI 00000000B
STWR PIEB2

LDWI 0FFH ; PWM period value = FFH "period time: (256) * (0.1uS*4) * (1) = 102.4uS" when 10Mhz
STWR T2PER ; (256)>>FFH / (0.1uS*4)>>TOSC / (1) = prescaler rate

LCALL SET_PAGE0
LDWI 00001111B ; Set CCP1 / CCP2 into PWM mode
STWR CCP1CTL
STWR CCP2CTL

LDWI 00000000B ; Prescaler rate 1:1 ; TMR2 off
STWR T2STA

CLRR TMR0
CLRR TMR2


PWM_LOOP: CLRWT

LDWI 00H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP PWM_LOOP

LDWI 01H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP PWM14

LDWI 02H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP PWM12

LDWI 03H
XORWR TMR0,W
BTSC STATUS,Z
LJUMP PWM11

LJUMP STAGE8_FSH

PWM_COMP: CLRWT
LCALL SET_PAGE0
BSR T2STA,2 ; Enable TMR2
LDR TMR0,W
XORWR TEMP0,W
BTSC STATUS,Z
LJUMP PWM_COMP
BCR T2STA,2 ; Disable TMR2
LJUMP PWM_LOOP

PWM14: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 00111111B ; Set duty cycle value = (1/4)*256 = 64
STWR CCP1L
STWR CCP2L
LJUMP PWM_COMP

PWM12: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 01111111B ; Set duty cycle value = (1/2)*256 = 128
STWR CCP1L
STWR CCP2L
LJUMP PWM_COMP

PWM11: LCALL SET_PAGE0
CLRWT
LDR TMR0,W
STWR TEMP0
COMR TEMP0,W
STWR RB
LDWI 11111111B ; Set duty cycle value = (1/1)*256 = 256
STWR CCP1L
STWR CCP2L
LJUMP PWM_COMP


STAGE8_FSH: CLRWT
LDR STAGE3T,W
STWR RB
COMR RB,1
LDWI 0FFH
STWR RC
SLEEP
LJUMP BEGIN


;.............................

; ===== COMMON SUB-PROGRAM BLOCK ===========================================================================
; ..... Sub_program : common delay time ..........................
DELAY: CLRWT ;*1
LDWI 0FFH ;*1
STWR DELAY_1 ;*1

DELAY1: LDWI 0FFH ;*256
STWR DELAY_2 ;*256
DELAY2: CLRWT ;*256*256
DECRSZ DELAY_2 ;*256*256
LJUMP DELAY2 ;*255*256

DECRSZ DELAY_1 ;*256
LJUMP DELAY1 ;*255
RET ;*1

; ..... Sub_program : PA shows how stage for TRIPLE ..............
TRIPLE: LDWI 03H
STWR STAGELP
TRIPLELP: LDR STAGE3T,W
STWR RB
COMR RB,1
LCALL DELAY
LDWI 0FFH
STWR RB
LCALL DELAY
DECRSZ STAGELP,1
LJUMP TRIPLELP
RET

TRIRC: LDWI 03H
STWR STAGELP
TRIRCLP: LDR TEMP1,W
STWR RC
COMR RC,1
LCALL DELAY
LDWI 0FFH
STWR RC
LCALL DELAY
DECRSZ STAGELP,1
LJUMP TRIRCLP
RET

TRIRB: LDWI 03H
STWR STAGELP
TRIRBLP: LDR TEMP1,W
STWR RB
COMR RB,1
LCALL DELAY
LDWI 0FFH
STWR RB
LCALL DELAY
DECRSZ STAGELP,1
LJUMP TRIRBLP
RET

; ..... Sub_program : Memory page selection ......................
SET_PAGE0: BCR STATUS,RBS0
RET

SET_PAGE1: BSR STATUS,RBS0
RET

; ..... Sub_program : RA.RB I/O mode selection ...................
SETRA_IN: LCALL SET_PAGE1
LDWI 0FFH
STWR CPIOA
LCALL SET_PAGE0
RET
SETRA_OUT: LCALL SET_PAGE1
CLRW
STWR CPIOA
LCALL SET_PAGE0
RET

SETRB_IN: LCALL SET_PAGE1
LDWI 0FFH
STWR CPIOB
LCALL SET_PAGE0
RET
SETRB_OUT: LCALL SET_PAGE1
CLRW
STWR CPIOB
LCALL SET_PAGE0
RET

SETRC_IN: LCALL SET_PAGE1
LDWI 0FFH
STWR CPIOC
LCALL SET_PAGE0
RET
SETRC_OUT: LCALL SET_PAGE1
CLRW
STWR CPIOC
LCALL SET_PAGE0
RET

SETRD_IN: LCALL SET_PAGE1
LDWI 0FFH
STWR CPIOD
LCALL SET_PAGE0
RET
SETRD_OUT: LCALL SET_PAGE1
CLRW
STWR CPIOD
LCALL SET_PAGE0
RET

SETRE_IN: LCALL SET_PAGE1
LDWI 0FFH
STWR CPIOE
LCALL SET_PAGE0
RET
SETRE_OUT: LCALL SET_PAGE1
CLRW
STWR CPIOE
LCALL SET_PAGE0
RET