DEMO PROGRAM MDT2060

; ===== DESCRIPTION ========================================================================================
; for IMD102 711 series: 1060 / 2060

; ===== REGISTER DEFINITION (RAM MAPPING) ==================================================================


; --- PAGE 0 -----------------------------------------------------------------------------------------------
; ......"SPECIAL"...........................................................................................
INDR_ADD EQU 00H ;00H Indirect Addressing Register
RTCC EQU 01H ;01H RTCC
PCL EQU 02H ;02H PC bit 7~0
STATUS EQU 03H ;03H STATUS
MSR EQU 04H ;04H MSR
RA EQU 05H ;05H PORT A
RB EQU 06H ;06H PORT B
;07H
;08H A/D control & status
;09H A/D conversion value
PCH EQU 0AH ;0AH PC bit 9.8
INTS EQU 0BH ;0BH Interrupt status


; ......"USER"..............................................................................................
STAGE EQU 0CH ;0CH Shows how stage
DELAY_1 EQU 0DH ;0DH Delay counter 1
DELAY_2 EQU 0EH ;0EH Delay counter 2
TEMP0 EQU 0FH ;0FH
TEMP1 EQU 10H ;10H Application register
TEMP2 EQU 11H ;11H
TEMP3 EQU 12H ;12H
TEMP4 EQU 13H ;13H
; --- PAGE 1 -----------------------------------------------------------------------------------------------

TMR EQU 81H ;81H Time mode
CPIOA EQU 85H ;85H Tris A
CPIOB EQU 86H ;86H Tris B
PSTA EQU 87H ;87H PRD & POR flag
;88H A/D pin control

; ===== STATUS DEFINITION ==================================================================================
C EQU 0
HC EQU 1
Z EQU 2
PF EQU 3
TF EQU 4
RBS0 EQU 5

; ===== OTHERS DEFINITION ==================================================================================
W EQU 0
PRDB EQU 0
PORB EQU 1

; ===== MAIN-PROGRAM BLOCK =================================================================================
; ----- 檢查 STATUS 暫存器的 B4(TF) 及 B3(PF), 依 RESET 原因作 DEMO 程式的流程控制 -------------------------
;if TF為是'0': PF為是'0'> 代表 IC 進入 sleep 後被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以進行跳關
; : PF為否'1'> 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至指定的副程式作 WDT 功能檢測
;if TF為否'1': PF為是'0'> 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序
; : PF為否'1'> Power on reset 或程式進行中作 MCLR reset


; ----- RESET VECTOR ---------------------------------------------------------------------------------------
ORG 00H ; 以下程式碼由 00H 的位址開始存入程式記憶體(ROM)
LJUMP BEGIN

; ----- INTERRUPT VECTOR -----------------------------------------------------------------------------------
ORG 04H
LCALL SET_PAGE0
LDWI 0F8H
STWR RTCC




BTSC INTS,0
LJUMP INTPBCHG

BTSC INTS,1
LJUMP INTEXTPB0

BTSC INTS,2
LJUMP INTRTCC

RTFI


ORG 10H
BEGIN:


LCALL SET_PAGE0
BTSS STATUS,TF ; check TF 判斷是否被 WDT reset, 0:是 1:否
LJUMP TF0 ; TF=0, IC 被 WDT reset, 跳至 'TF0 副程式'

TF1: BTSS STATUS,PF ; TF=1, IC 未被 WDT reset, check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP PF0 ; ____PF=0, 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序

LJUMP STAGE1 ; ____PF=1, Power on reset, 跳至 'STAGE1 副程式'


TF0: LCALL SETRA_OUT ; 因為 TF=0, IC 被 WDT reset
BTSC STATUS,PF ; check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP TF0PF1 ; ____PF=1, 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至 'TF0PF1 副程式' 進行 WDT test
LCALL SETRB_OUT
SLEEP ; ____PF=0, 代表 IC 進入 sleep 後又被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以跳至 'PF0 副程式',
LJUMP BEGIN ; 並以 STAGE 暫存器之累加值進行關卡轉換

TF0PF1: CLRWT
LJUMP BEGIN1A ; 跳至 'BEGIN1A 副程式' 進行 WDT test


PF0: LDR STAGE,W ; 將 STAGE 暫存器累加值與目前 PC 值相加
ADDWR PCL,1 ; 相加後的 PC 值指向欲測試之關卡
LJUMP STAGE2 ; RAM testing
LJUMP STAGE3 ; RTCC testing
LJUMP STAGE4 ; WDT testing
LJUMP STAGE5 ; Interrupt testing





LJUMP STAGE1 ; I/O testing

; ----- STAGE1 I/O testing ---------------------------------------------------------------------------------





























STAGE1: ANDWI 00001111B
XORWR RA,W
BTSC STATUS,Z
LJUMP FAIL_RAIN
LDWI 10101010B
ANDWI 11111111B
XORWR RB,W
BTSC STATUS,Z
LJUMP FAIL_RBIN

LCALL SETRA_OUT
LCALL SETRB_OUT
LDWI 0FFH
STWR RB

CLRR STAGE
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

CLRR TEMP3
ADDRA: CLRWT
LDR TEMP3,W
ADDWR PCL,1
LJUMP RA1H
LJUMP RA3H
LJUMP RA7H
LJUMP RAFH
LJUMP RA1FH
LJUMP IOEND

OUTTEST: CLRR RB
BSR STATUS,C
OUTLOOP: CLRWT
RRR RB
LCALL DELAY
BTSS STATUS,C
LJUMP OUTLOOP
INCR TEMP3
LJUMP ADDRA


RA1H: LDWI 01H
STWR RA
COMR RA,1
LJUMP OUTTEST

RA3H: LDWI 03H
STWR RA
COMR RA,1
LJUMP OUTTEST

RA7H: LDWI 07H
STWR RA
COMR RA,1
LJUMP OUTTEST

RAFH: LDWI 0FH
STWR RA
COMR RA,1
LJUMP OUTTEST

RA1FH: LDWI 01FH
STWR RA
COMR RA,1
LJUMP OUTTEST



IOEND: CLRWT
INCR STAGE,W
STWR RA
STWR RB
COMR RA,1
COMR RB,1
SLEEP
LJUMP BEGIN

FAIL_RAIN: CLRW
CPIO RB
LDWI 0AH
STWR RB
SLEEP
LJUMP BEGIN

FAIL_RBIN: CLRW
CPIO RB
LDWI 0BH
STWR RB
SLEEP
LJUMP BEGIN


; ----- STAGE2 RAM testing ---------------------------------------------------------------------------------
STAGE2: LCALL SETRA_OUT
LCALL SETRB_OUT
INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

LDWI 10H ; Initial address 10H
STWR MSR ; MSR point
STWR TEMP1
LCALL TRIRB
LDR MSR,W
STWR TEMP0 ; "10H" Compare value
BANK0: LDR MSR,W ; Load the address where MSR point to
STWR INDR_ADD ; Save address value to itself
LDR TEMP0,W
XORWR INDR_ADD,W
BTSS STATUS,Z
LJUMP RAMFAIL
LDR MSR,W
STWR RB
COMR RB,1
LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
INCR TEMP0,1 ; compare value +1
XORWI 02FH
BTSS STATUS,Z
LJUMP BANK0

DECR TEMP0,W
STWR TEMP1
LCALL TRIRB

LDWI 10H
STWR 10H

CLRWT
INCR STAGE,W
STWR RA
STWR RB
COMR RA,1
COMR RB,1
SLEEP
LJUMP BEGIN

RAMFAIL: LDR MSR,W
STWR RB
COMR RB,1
SLEEP
LJUMP BEGIN

; ----- STAGE4 WDT testing --------------------------------------------------------------------------------
STAGE4: LCALL SETRA_OUT
LCALL SETRB_OUT
INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

BEGIN1: CLRWT ; Set initial value
CLRR TEMP2 ; Set PC ++ register
LDWI 08H ; Set testing cycle count
STWR TEMP3
LDWI 00001000B ; Set WDT RATE 1
TMODE
LCALL RBHI ; RB Hi-byte light on
LDWI 01H ; RA shows 1
STWR RA
COMR RA,1
LJUMP DUMMY ; Dummy for WDT testing & Set 10H.11H.12H to save count value

BEGIN1A: CLRWT
LCALL SETRA_OUT
LCALL SETRB_OUT
DECRSZ TEMP3,1 ; Check tesing cycle
LJUMP BEGIN2 ; Countinue testing
CLRWT
LJUMP WDTEND ; Cycle finish to end stage4


BEGIN2: CLRWT
LDR TEMP2,W
ADDWR PCL,1
LJUMP R2
LJUMP R4
LJUMP R8
LJUMP R16
LJUMP R32
LJUMP R64
LJUMP R128
LJUMP WDTEND

R2: LDWI 00001001B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 02H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R4: LDWI 00001010B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 03H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R8: LDWI 00001011B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 04H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R16: LDWI 00001100B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 05H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R32: LDWI 00001101B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 06H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R64: LDWI 00001110B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 07H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

R128: LDWI 00001111B
TMODE
LCALL SETRA_OUT
LCALL SETRB_OUT
SWAPR RB
LDWI 08H
STWR RA
COMR RA,1
INCR TEMP2,1
LJUMP DUMMY

WDTEND: CLRWT
LCALL SETRA_OUT
LCALL SETRB_OUT
INCR STAGE,W
STWR RA
STWR RB
COMR RA,1
COMR RB,1
SLEEP
LJUMP BEGIN


DUMMY: CLRR 18H
CLRR 19H
CLRR 1AH
CLRR 1BH
CLRR 1CH
CLRR 1DH
CLRR 1EH
CLRR 1FH
CLRWT
B0: INCRSZ 1FH ; 1 * 256 * ( 255 * 255 )
LJUMP B0 ; 2 * 255 * ( 255 * 255 )
B1: INCRSZ 1EH ; 1 * 256 * 255
LJUMP B0 ; 2 * 255 * 255
B2: INCRSZ 1DH ; 1 * 256
LJUMP B0 ; 2 * 255
SLEEP
LJUMP BEGIN

RBHI: LDWI 11110000B
STWR RB
COMR RB,1
RET

; ----- STAGE3 RTCC testing --------------------------------------------------------------------------------
STAGE3: LCALL SETRA_OUT
LCALL SETRB_OUT
INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

CLRR RTCC

LDWI 00111000B ; set 1_external rtcc 2_hi to lo edge 3_not assign rtcc 4_no rate
TMODE

EXTERHI: CLRWT
LDR RTCC,W ; push bottom 0~7 by Hi to Lo trigger
STWR TEMP2
COMR TEMP2,W
STWR RB
LDWI 00000111B
SUBWR RTCC,W
BTSS STATUS,Z
LJUMP EXTERHI

LDWI 00101000B ; set 1_external rtcc 2_lo to hi edge 3_not assign rtcc 4_no rate
TMODE

EXTERLO: CLRWT
LDR RTCC,W ; push bottom 8~F by Lo to Hi trigger
STWR TEMP2
COMR TEMP2,W
STWR RB
LDWI 00001111B
SUBWR RTCC,W
BTSS STATUS,Z
LJUMP EXTERLO

LDWI 0FFH
STWR RB
BSR STATUS,C
BCR RB,0

LDWI 00000111B ; 1:256
TMODE
LCALL RTCCSET

LDWI 00000110B ; 1:128
TMODE
LCALL RTCCSET

LDWI 00000101B ; 1: 64
TMODE
LCALL RTCCSET

LDWI 00000100B ; 1: 32
TMODE
LCALL RTCCSET

LDWI 00000011B ; 1: 16
TMODE
LCALL RTCCSET

LDWI 00000010B ; 1: 8
TMODE
LCALL RTCCSET

LDWI 00000001B ; 1: 4
TMODE
LCALL RTCCSET

LDWI 00000000B ; 1: 2
TMODE
LCALL RTCCSET


CLRR RTCC
LDWI 00000111B ; 1:256
TMODE
CLRWT
LDWI 00001111B
TMODE
INCR STAGE,W
STWR RA
STWR RB
COMR RA,1
COMR RB,1
SLEEP
LJUMP BEGIN

RTCCSET: CLRR RTCC ; wait delayck time 143.2 uS to check rtcc value
LCALL DELAYCK ; freq. 10 MHz , RTCC timer = 10/4 =2.5 MHz
LDR RTCC,W
LCALL DELAYRT ; dummy delay
RLR RB,1
RTIW 00H



DELAYCK: LDWI 007H ; * 1 = 1 = 1 1: 2 = 143.2 / 0.8 = 179 ~ 179 D = B3 H
STWR DELAY_1 ; * 1 = 1 = 1 1: 4 = 143.2 / 1.6 = 89.5 ~ 90 D = 5A H
; 1: 8 = 143.2 / 3.2 = 44.75 ~ 45 D = 2D H
DELAYCK1: LDWI 010H ; * 7 = 7 = 7 1: 16 = 143.2 / 6.4 = 22.375 ~ 22 D = 15 H
STWR DELAY_2 ; * 7 = 7 = 7 1: 32 = 143.2 / 12.8 = 11.1875 ~ 11 D = 0B H
DELAYCK2: CLRWT
DECRSZ DELAY_2 ; * 16 * 7 = 112 = 112 1: 64 = 143.2 / 25.6 = 5.59375 ~ 6 D = 06 H
LJUMP DELAYCK2 ; * 15 * 7 = 105 * 2 = 210 1: 128 = 143.2 / 51.2 = 2.796875 ~ 3 D = 03 H
; 1: 256 = 143.2 / 102.4 = 1.3984375 ~ 1 D = 01 H
DECRSZ DELAY_1 ; * 7 = 7 = 7
LJUMP DELAYCK1 ; * 6 = 6 * 2 = 12
RTIW 00H ; * 1 = 1 = 1 TOTAL = 358 instruction time / 358 * 0.4uS = 143.2uS



DELAYRT: STWR DELAY_1 ;

DELAYRT1: LDWI 01FH ;
STWR DELAY_2 ;

DELAYRT2: CLRWT
LDWI 0FFH ;
STWR TEMP3 ;

DELAYRT3: CLRWT
DECRSZ TEMP3 ;
LJUMP DELAYRT3 ;

DECRSZ DELAY_2 ;
LJUMP DELAYRT2 ;

DECRSZ DELAY_1 ;
LJUMP DELAYRT1 ;

RTIW 00H ;

; ----- STAGE 5. Interrupt testing from 3 source except A/D INT(0BH.81H) -----------------------------------
; Method

STAGE5:



LCALL SET_PAGE0 ; Set RAM page0
LCALL SETRA_OUT ; Add 1 to stage, this stage value should be 4, when reset add to PCL set jump stage
LCALL SETRB_OUT ; Add 1 to stage, this stage value should be 4, when reset add to PCL set jump stage
INCR STAGE,1 ; Stage value add 1 = 5 to W and output on PA
INCR STAGE,W ; Stage value add 1 = 5 to W and output on PA
STWR TEMP1
LCALL TRIPLE

CLRR RB ; Clear PB

LCALL SETRB_IN ; Set PB input mode
LDR RB,1

LDWI 00111000B ; Set TER: PB pull-hi enable / PB0 Hi > Lo trig to INT enable
TMODE

LDWI 0F8H
STWR RTCC
LDWI 10111000B ; Set INT: total on / All interrupt enable & Clear 3 source flag except A/D
STWR INTS

LCALL SET_PAGE1
BSR CPIOA,4
LCALL SET_PAGE0

LOOPINT: LDR RB,1
LDWI 00001010B
STWR RA
LCALL DELAY
LDR RB,1
LDWI 00001010B
STWR RA
LCALL DELAY
LJUMP LOOPINT

INTPASS: LCALL SET_PAGE0
LDWI 00000000B
STWR INTS
LCALL SETRB_OUT

CLRWT
LCALL SET_PAGE0 ; Select page 0
LCALL SETRA_OUT
LCALL SETRB_OUT
LDWI 06H
STWR RA
STWR RB
COMR RA,1
COMR RB,1
SLEEP
LJUMP BEGIN

; ..... INT sub-program : PB7~PB4 pin change occured .............
INTPBCHG: LDR RA,W
STWR TEMP3
LCALL SETRB_OUT
LDWI 01H
STWR TEMP1
LCALL TRIRA
LCALL SETRB_IN
LCALL SET_PAGE0
LDR RB,1
LDR TEMP3,W
STWR RA

LDWI 10111000B
STWR INTS
LDWI 0F8H
STWR RTCC
RTFI

; ..... INT sub-program : PB0 external INT signal Hi > Lo ........
INTEXTPB0: LDR RA,W
STWR TEMP3
LCALL SETRB_OUT
LDWI 02H
STWR TEMP1
LCALL TRIRA
LCALL SETRB_IN
LCALL SET_PAGE0
LDR RB,1
LDR TEMP3,W
STWR RA

LDWI 10111000B
STWR INTS
LDWI 0F8H
STWR RTCC
RTFI

; ..... INT sub-program : Ext RTCC signal Lo > Hi for 3 times ....
INTRTCC: LDR RA,W
STWR TEMP3
LCALL SETRB_OUT
LDWI 03H
STWR TEMP1
LCALL TRIRA
LCALL SETRB_IN
LCALL SET_PAGE0
LDR RB,1
LDR TEMP3,W
STWR RA

LDWI 10111000B
STWR INTS
LDWI 0F8H
STWR RTCC
RTFI














































































































; ===== COMMON SUB-PROGRAM BLOCK ===========================================================================
; ..... Sub_program : common delay time ..........................
DELAY: CLRWT ;*1
LDWI 0FFH ;*1
STWR DELAY_1 ;*1

DELAY1: LDWI 0FFH ;*256
STWR DELAY_2 ;*256
DELAY2: CLRWT ;*256*256
DECRSZ DELAY_2 ;*256*256
LJUMP DELAY2 ;*255*256

DECRSZ DELAY_1 ;*256
LJUMP DELAY1 ;*255
RET ;*1

; ..... Sub_program : PA shows how stage for TRIPLE ..............
TRIPLE: LDWI 03H
STWR TEMP0
TWICELP: LDR TEMP1,W
STWR RA
STWR RB
COMR RA,1
COMR RB,1
LCALL DELAY
LDWI 0FFH
STWR RA
STWR RB
LCALL DELAY
DECRSZ TEMP0,1
LJUMP TWICELP
RET

TRIRA: LDWI 03H
STWR TEMP0
TRIRALP: LDR TEMP1,W
STWR RA
COMR RA,1
LCALL DELAY
LDWI 0FFH
STWR RA
LCALL DELAY
DECRSZ TEMP0,1
LJUMP TRIRALP
RET

TRIRB: LDWI 03H
STWR TEMP0
TRIRBLP: LDR TEMP1,W
STWR RB
COMR RB,1
LCALL DELAY
LDWI 0FFH
STWR RB
LCALL DELAY
DECRSZ TEMP0,1
LJUMP TRIRBLP
RET


; ..... Sub_program : Memory page selection ......................
SET_PAGE0: BCR STATUS,RBS0
RET

SET_PAGE1: BSR STATUS,RBS0
RET

; ..... Sub_program : RA.RB I/O mode selection ...................
SETRA_IN: LDWI 0FFH
CPIO RA
RET

SETRA_OUT: CLRW
CPIO RA
RET

SETRB_IN: LDWI 0FFH
CPIO RB
RET

SETRB_OUT: CLRW
CPIO RB
RET

END