DEMO PROGRAM MDT10P55A4

; ===== DESCRIPTION ========================================================================================
; for IMD101 5X series: 10C55A4 / 10P55A4

; ===== REGISTER DEFINITION (RAM MAPPING) ==================================================================



; ......"SPECIAL"...........................................................................................
INDR_ADD EQU 00H ;00H Indirect Addressing Register
RTCC EQU 01H ;01H RTCC
PC EQU 02H ;02H PC
STATUS EQU 03H ;03H STATUS
MSR EQU 04H ;04H MSR
RA EQU 05H ;05H NO EXIST
RB EQU 06H ;06H PORT B
RC EQU 07H ;07H PORT C






; ......"USER"..............................................................................................
STAGE EQU 08H ;08H
DELAY_1 EQU 09H ;09H
DELAY_2 EQU 0AH ;0AH
TEMP0 EQU 0BH ;0BH
TEMP1 EQU 0CH ;0CH
TEMP2 EQU 0DH ;0DH
TEMP3 EQU 0EH ;0EH









; ===== STATUS DEFINITION ==================================================================================
C EQU 0
HC EQU 1
Z EQU 2
PF EQU 3
TF EQU 4
PCWUF EQU 7

; ===== OTHERS DEFINITION ==================================================================================
W EQU 0



; ===== MAIN-PROGRAM BLOCK =================================================================================
; ----- 檢查 STATUS 暫存器的 B4(TF) 及 B3(PF), 依 RESET 原因作 DEMO 程式的流程控制 -------------------------
;if TF為是'0': PF為是'0'> 代表 IC 進入 sleep 後被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以進行跳關
; : PF為否'1'> 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至指定的副程式作 WDT 功能檢測
;if TF為否'1': PF為是'0'> 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序
; : PF為否'1'> Power on reset 或程式進行中作 MCLR reset



ORG 00H ; 以下程式碼由 00H 的位址開始存入程式記憶體(ROM)

BEGIN: BTSS STATUS,TF ; check TF 判斷是否被 WDT reset, 0:是 1:否
LJUMP TF0 ; TF=0, IC 被 WDT reset, 跳至 'TF0 副程式'

TF1: BTSS STATUS,PF ; TF=1, IC 未被 WDT reset, check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP PF0 ; ____PF=0, 代表 IC 進入 sleep 後在 WDT reset 前被 MCLR reset, 並執行跳關程序

LJUMP STAGE1 ; ____PF=1, Power on reset, 跳至 'STAGE1 副程式'


TF0: ; 因為 TF=0, IC 被 WDT reset
BTSC STATUS,PF ; check PF 判斷是否進入 sleep 狀態, 0:是 1:否
LJUMP TF0PF1 ; ____PF=1, 代表 IC 尚未進入 sleep 便被 WDT reset, 跳至 'TF0PF1 副程式' 進行 WDT test

CLRW
CPIO RC
LDWI 01111111B
TMODE
LDR RB,1
SLEEP ; ____PF=0, 代表 IC 進入 sleep 後又被 WDT reset, 為閒置狀態, 須再次進入 sleep 等待 MCLR reset 以跳至 'PF0 副程式',
; 並以 STAGE 暫存器之累加值進行關卡轉換

TF0PF1: CLRWT
LJUMP BEGIN1A ; 跳至 'BEGIN1A 副程式' 進行 WDT test


PF0: LDR STAGE,W ; 將 STAGE 暫存器累加值與目前 PC 值相加
ADDWR PC,1 ; 相加後的 PC 值指向欲測試之關卡
LJUMP STAGE2 ; RAM testing
LJUMP STAGE3 ; RTCC testing
LJUMP STAGE4 ; WDT testing
LJUMP STAGE1 ; I/O testing

; ----- STAGE1 I/O testing ---------------------------------------------------------------------------------
STAGE1: LDWI 10101010B
STWR RB
STWR RC

ANDWI 00111111B
XORWR RB,W
BTSC STATUS,Z
LJUMP FAIL_RBIN
LDWI 10101010B
ANDWI 00111111B
XORWR RC,W
BTSC STATUS,Z
LJUMP FAIL_RCIN






CLRW
CPIO RB
CPIO RC

CLRR RB
CLRR RC


CLRR STAGE
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

CLRR TEMP3
ADDRA: CLRWT
LDR TEMP3,W
ADDWR PC,1
LJUMP RB1H
LJUMP RB3H
LJUMP RB7H
LJUMP IOEND

OUTTEST: CLRR RC

BSR RC,5
LOOPRC: CLRWT
LCALL DELAY
RRR RC
BTSS STATUS,C
LJUMP LOOPRC





INCR TEMP3,1
LJUMP ADDRA


RB1H: LDWI 00000001B
STWR RB
COMR RB,1
LJUMP OUTTEST

RB3H: LDWI 00000011B
STWR RB
COMR RB,1
LJUMP OUTTEST

RB7H: LDWI 00000111B
STWR RB
COMR RB,1
LJUMP OUTTEST

IOEND: CLRWT
INCR STAGE,W
STWR RC
COMR RC,1
LDWI 3FH
CPIO RB
LDR RB,1
LDWI 00000000B
TMODE
SLEEP

FAIL_RBIN: CLRW
CPIO RC
LDWI 0AH
STWR RC
SLEEP

FAIL_RCIN: CLRW
CPIO RC
LDWI 0BH
STWR RC
SLEEP







; ----- STAGE2 RAM testing ---------------------------------------------------------------------------------
STAGE2: CLRW
CPIO RB
CPIO RC

INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

LDWI 0FH ; Initial address 0FH
STWR MSR ; MSR point
STWR TEMP0 ; "0FH" Compare value
LDWI 080H ; Make compare value to match real saving value
ADDWR TEMP0,1 ; "8FH"
LCALL SHOWADD
BANK0: LDR MSR,W ; Load the address where MSR point to
STWR INDR_ADD ; Save address value to itself
LDR TEMP0,W
XORWR INDR_ADD,W
BTSS STATUS,Z
LJUMP RAMFAIL

LDR MSR,W
STWR TEMP2
LCALL SHOWRBRC

LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
INCR TEMP0,1 ; compare value +1
XORWI 09FH
BTSS STATUS,Z
LJUMP BANK0

LDWI 30H ; Initial address 30H
STWR MSR ; MSR point
STWR TEMP0 ; "30H" Compare value
LDWI 80H ; Make compare value to match real saving value
ADDWR TEMP0,1 ; "B0H"
BANK123: LDR MSR,W ; Load the address where MSR point to
STWR INDR_ADD ; Save address value to itself
LDR TEMP0,W
XORWR INDR_ADD,W
BTSS STATUS,Z
LJUMP RAMFAIL

LDR MSR,W
STWR TEMP2
LCALL SHOWRBRC

LCALL DELAY
LDR MSR,W
INCR MSR,1 ; Indirect address +1
BSR MSR,4
INCR TEMP0,1 ; compare value +1
BSR TEMP0,4
XORWI 0FFH
BTSS STATUS,Z
LJUMP BANK123

LDWI 0FFH
STWR RB
STWR RC
LCALL DELAY

LDR TEMP3,W
STWR TEMP0
LCALL DELAY
LCALL SHOWADD

CLRWT
INCR STAGE,W
STWR RC
COMR RC,1
LDWI 3FH
CPIO RB
LDR RB,1
LDWI 00000000B
TMODE
SLEEP

RAMFAIL: LDR MSR,W
STWR TEMP2
LCALL SHOWRBRC
SLEEP


SHOWADD: LDWI 03H
STWR TEMP1
RESHOW: LDR TEMP0,W
STWR TEMP2
LCALL SHOWRBRC
LCALL DELAY
LDWI 0FFH
STWR RB
STWR RC
LCALL DELAY
DECRSZ TEMP1
LJUMP RESHOW
RTIW 00H


SHOWRBRC: LDR TEMP2,W
STWR TEMP3
ANDWI 00001111B
STWR RC
COMR RC,1
RRR TEMP2,1
RRR TEMP2,1
RRR TEMP2,1
RRR TEMP2,W
ANDWI 00001111B
STWR RB
COMR RB,1
RET


; ----- STAGE4 WDT testing --------------------------------------------------------------------------------
STAGE4: CLRW
CPIO RB
CPIO RC

INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE

BEGIN1: CLRWT ; Set initial value
CLRR TEMP2 ; Set PC ++ register
LDWI 08H ; Set testing cycle count
STWR TEMP3
LDWI 00001000B ; Set WDT RATE 1
TMODE
LCALL RCHI2 ; RB Hi-byte light on
LDWI 11111110B ; RA shows 1
STWR RB
LJUMP DUMMY ; Dummy for WDT testing & Set 10H.11H.12H to save count value

BEGIN1A: CLRWT
DECRSZ TEMP3,1 ; Check tesing cycle
LJUMP BEGIN2 ; Countinue testing
CLRWT
LJUMP WDTEND ; Cycle finish to end stage4


BEGIN2: CLRWT
LDR TEMP2,W
ADDWR PC,1
LJUMP R2
LJUMP R4
LJUMP R8
LJUMP R16
LJUMP R32
LJUMP R64
LJUMP R128
LJUMP WDTEND

R2: LDWI 00001001B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCLO2

LDWI 11111101B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

R4: LDWI 00001010B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCHI2

LDWI 11111100B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

R8: LDWI 00001011B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCLO2

LDWI 11111011B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

R16: LDWI 00001100B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCHI2

LDWI 11111010B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

R32: LDWI 00001101B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCLO2

LDWI 11111001B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

R64: LDWI 00001110B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCHI2

LDWI 11111000B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

R128: LDWI 00001111B
TMODE
CLRW
CPIO RB
CPIO RC

LCALL RCLO2

LDWI 11110111B
STWR RC
INCR TEMP2,1
LJUMP DUMMY

WDTEND: CLRWT
CLRW
CPIO RB
CPIO RC

INCR STAGE,W
STWR RC
COMR RC,1
LDWI 3FH
CPIO RB
LDR RB,1
LDWI 00000000B
TMODE
SLEEP


DUMMY: CLRR 10H
CLRR 11H
CLRR 12H
CLRR 13H
CLRR 14H
CLRR 15H
CLRR 16H
CLRR 17H
CLRWT
B0: INCRSZ 17H ; 1 * 256 * ( 255 * 255 )
LJUMP B0 ; 2 * 255 * ( 255 * 255 )
B1: INCRSZ 16H ; 1 * 256 * 255
LJUMP B0 ; 2 * 255 * 255
B2: INCRSZ 15H ; 1 * 256
LJUMP B0 ; 2 * 255
SLEEP

RCHI2: LDWI 11111101B
STWR RB
RET

RCLO2: LDWI 11111110B
STWR RB
RET



; ----- STAGE3 RTCC testing --------------------------------------------------------------------------------
STAGE3: LDWI 00111000B
CPIO RB
LDWI 00100000B
CPIO RC

INCR STAGE,1
INCR STAGE,W
STWR TEMP1
LCALL TRIPLE


CLRR RTCC
LDWI 10111000B ; set 1_external rtcc 2_hi to lo edge 3_not assign rtcc 4_no rate
TMODE

EXTERHI: CLRWT
LDR RTCC,W ; push bottom 0~7 by Hi to Lo trigger
STWR TEMP2
COMR TEMP2,W
STWR RC
LDWI 00000111B
SUBWR RTCC,W
BTSS STATUS,Z
LJUMP EXTERHI

LDWI 10101000B ; set 1_external rtcc 2_lo to hi edge 3_not assign rtcc 4_no rate
TMODE

EXTERLO: CLRWT
LDR RTCC,W ; push bottom 8~F by Lo to Hi trigger
STWR TEMP2
COMR TEMP2,W
STWR RC
LDWI 00001111B
SUBWR RTCC,W
BTSS STATUS,Z
LJUMP EXTERLO

LDWI 0FFH
STWR RB
STWR RC
BSR STATUS,C
BCR RC,0
CLRR RTCC

LDWI 00000111B ; 1:256
TMODE
LCALL RTCCSETRC

LDWI 00000110B ; 1:128
TMODE
LCALL RTCCSETRC

LDWI 00000101B ; 1: 64
TMODE
LCALL RTCCSETRC

LDWI 00000100B ; 1: 32
TMODE
LCALL RTCCSETRC

LDWI 00000011B ; 1: 16
TMODE
LCALL RTCCSETRC
LDWI 0FFH
STWR RC
BSR STATUS,C
BCR RB,0

LDWI 00000010B ; 1: 8
TMODE
LCALL RTCCSETRB

LDWI 00000001B ; 1: 4
TMODE
LCALL RTCCSETRB

LDWI 00000000B ; 1: 2
TMODE
LCALL RTCCSETRB


CLRR RTCC
LDWI 00000111B ; 1:256
TMODE
CLRWT
LDWI 00001111B
TMODE

CLRWT
CLRW
CPIO RC
INCR STAGE,W
STWR RC
COMR RC,1
LDWI 3FH
CPIO RB
LDR RB,1
LDWI 00000000B
TMODE
SLEEP

RTCCSETRC: CLRR RTCC ; wait delayck time 143.2 uS to check rtcc value
LCALL DELAYCK ; freq. 10 MHz , RTCC timer = 10/4 =2.5 MHz
LDR RTCC,W
LCALL DELAYRT ; dummy delay
BSR STATUS,C
RLR RC,1
RTIW 00H

RTCCSETRB: CLRR RTCC ; wait delayck time 143.2 uS to check rtcc value
LCALL DELAYCK ; freq. 10 MHz , RTCC timer = 10/4 =2.5 MHz
LDR RTCC,W
LCALL DELAYRT ; dummy delay
BSR STATUS,C
RLR RB,1
RTIW 00H


DELAYCK: LDWI 007H ; * 1 = 1 = 1 1: 2 = 143.2 / 0.8 = 179 ~ 179 D = B3 H
STWR DELAY_1 ; * 1 = 1 = 1 1: 4 = 143.2 / 1.6 = 89.5 ~ 90 D = 5A H
; 1: 8 = 143.2 / 3.2 = 44.75 ~ 45 D = 2D H
DELAYCK1: LDWI 010H ; * 7 = 7 = 7 1: 16 = 143.2 / 6.4 = 22.375 ~ 22 D = 15 H
STWR DELAY_2 ; * 7 = 7 = 7 1: 32 = 143.2 / 12.8 = 11.1875 ~ 11 D = 0B H
DELAYCK2: CLRWT
DECRSZ DELAY_2 ; * 16 * 7 = 112 = 112 1: 64 = 143.2 / 25.6 = 5.59375 ~ 6 D = 06 H
LJUMP DELAYCK2 ; * 15 * 7 = 105 * 2 = 210 1: 128 = 143.2 / 51.2 = 2.796875 ~ 3 D = 03 H
; 1: 256 = 143.2 / 102.4 = 1.3984375 ~ 1 D = 01 H
DECRSZ DELAY_1 ; * 7 = 7 = 7
LJUMP DELAYCK1 ; * 6 = 6 * 2 = 12
RTIW 00H ; * 1 = 1 = 1 TOTAL = 358 instruction time / 358 * 0.4uS = 143.2uS



DELAYRT: STWR DELAY_1 ;

DELAYRT1: LDWI 01FH ;
STWR DELAY_2 ;

DELAYRT2: CLRWT
LDWI 0FFH ;
STWR TEMP3 ;

DELAYRT3: CLRWT
DECRSZ TEMP3 ;
LJUMP DELAYRT3 ;

DECRSZ DELAY_2 ;
LJUMP DELAYRT2 ;

DECRSZ DELAY_1 ;
LJUMP DELAYRT1 ;

RTIW 00H ;



; ===== COMMON SUB-PROGRAM BLOCK ===========================================================================
DELAY: CLRWT ;*1
LDWI 0FFH ;*1
STWR DELAY_1 ;*1

DELAY1: LDWI 0FFH ;*256
STWR DELAY_2 ;*256
DELAY2: CLRWT ;*256*256
DECRSZ DELAY_2 ;*256*256
LJUMP DELAY2 ;*255*256

DECRSZ DELAY_1 ;*256
LJUMP DELAY1 ;*255
RET ;*1

TRIPLE: LDWI 03H
STWR TEMP0
TWICELP: LDR TEMP1,W
STWR RB
COMR RB,1
STWR RC
COMR RC,1


LCALL DELAY
LDWI 0FFH
STWR RB
STWR RC

LCALL DELAY
DECRSZ TEMP0,1
LJUMP TWICELP
RET


ORG 1FFH
LJUMP BEGIN
ORG 3FFH
LJUMP BEGIN
ORG 7FFH
LJUMP BEGIN

END